Title: | Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics |
Authors: | Bin, Shu-Yung Lin, Shih-Feng Cheng, Ya-Ching Liau, Wen-Rong Hou, Alex Chao, Mango C. -T. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | Array test-structure;model-fitting;process monitor;SRAM characterization;test-time reduction |
Issue Date: | 1-Feb-2016 |
Abstract: | An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor\'s characteristics. This paper presents a model-fitting framework to predict the average read/write metrics of the SRAM cells in a lithography shot using only the measured transistor characteristics. The proposed framework is validated through the measurement result of 4750 samples of a 128-bit SRAM-array test structure implemented in a United Microelectronics Corporation 28-nm process technology. The experimental results show that the learned models can achieve at least 97.77% R-square on fitting the shot-level read static noise margin, write margin, and read current based on 2375-sample testing data. |
URI: | http://dx.doi.org/10.1109/TVLSI.2015.2418998 http://hdl.handle.net/11536/129641 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2015.2418998 |
Journal: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 24 |
Begin Page: | 625 |
End Page: | 637 |
Appears in Collections: | Articles |