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dc.contributor.authorMAA, JJen_US
dc.contributor.authorWU, CYen_US
dc.date.accessioned2014-12-08T15:03:14Z-
dc.date.available2014-12-08T15:03:14Z-
dc.date.issued1995-08-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.398665en_US
dc.identifier.urihttp://hdl.handle.net/11536/1791-
dc.description.abstractThe formulation, verification, and application of a new simplified 2-D threshold voltage model for n-MOSFET's with nonuniformly doped substrate profile are provided, in which the averaged normal field at the Si/SiO2 interface in the active channel is quoted from a simplified solution of two-dimensional Poisson equation using the Green function technique. Starting with the expression of this average normal field, a simple threshold-voltage model for short-channel n-MOSFET's with nonuniformly doped substrate profile is explicitly expressed in terms of device structures and terminal voltages by considering parabolic source-drain boundary potentials. Moreover, the effects of the junction depth on the threshold voltage are examined in detail. It is shown that the DLBL effect cannot be completely eliminated by simply increasing the substrate doping concentration. Comparisons among developed model, 2-D numerical analysis, and experimental data have been made and the accuracy of the developed analytical model has been verified. In addition, a direct extension of our model to the case of uniformly doped substrates leads to a new constraint equation for device miniaturization.en_US
dc.language.isoen_USen_US
dc.titleA NEW SIMPLIFIED THRESHOLD-VOLTAGE MODEL FOR N-MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE AND ITS APPLICATION TO MOSFETS MINIATURIZATIONen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.398665en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume42en_US
dc.citation.issue8en_US
dc.citation.spage1487en_US
dc.citation.epage1494en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1995RJ15000013-
dc.citation.woscount9-
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