應用於數位電視之H.264/AVC背景適應性二元算術解碼器

Abstract

在本論文中，我們提出一個高生產率的以記憶體為基礎的背景適應性二元算數解碼器，我們的提案由一個背景模型的399x7位元雙埠靜態記憶體及列儲存的120x208位元的單埠靜態記憶體所實現，我們將提供三個方法來改善背景適應性二元算數解碼器的生產率以克服劃分一連串區間值所帶來的資料相依，我們所提出來的架構可以為層次4.0達到平均每秒鐘處理244,800個巨方塊，因此，可以播放1080HD格式每秒三十張畫面的影像，基於0.13微米聯華電子互補式金氧半導體製程， 我們的背景適應性二元算數解碼器設計需要包含SRAM 163,573個邏輯閘，並運作在200MHz的時脈之下。

In this thesis, we propose a high-throughput RAM-based Context Adaptive Binary Arithmetic Decoder (CABAD). Our proposal is realized by one 399x7 bits two-port SRAM for the context model and one 120x208 bits single-port SRAM for row-storage of the syntax element. We will offer three methods to improve the throughput of CABAD in order to overcome the data dependency of the sub-division intervals. Our proposed architecture can achieve 244,800 macroblocks (MB) per second in average for level 4.0. Therefore, it can play 1080HD video at 30 fps. Based on 0.13µm UMC CMOS Process, our CABAD design needs 163,573 gates with SRAM and operates at 200MHz.