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dc.contributor.authorChen-Yi, Leeen_US
dc.contributor.authorChien-Ching, Linen_US
dc.contributor.authorChia-Cho, Wuen_US
dc.date.accessioned2014-12-16T06:16:18Z-
dc.date.available2014-12-16T06:16:18Z-
dc.date.issued2004-12-23en_US
dc.identifier.govdocH03M013/03zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105758-
dc.description.abstractAn algorithm for a memory-based Viterbi decoder is disclosed in the invention, which employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the algorithm of the invention is to save the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, and thus the power consumption made by the memory read operations would be largely reduced. Besides, before the path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. In conclusion, the invention is capable of reducing the number of memory access operations and the power consumption by employing the mechanisms of path matching and path prediction.zh_TW
dc.language.isozh_TWen_US
dc.titleAlgorithm for a memory-based Viterbi decoderzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20040261005zh_TW
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