| 標題: | 提升積體電路栓鎖防疫能力之設計方法與實現 DESIGN AND IMPLEMENTATION TO IMPROVE LATCHUP IMMUNITY OF CMOS INTEGRATED CIRCUITS |
| 作者: | 蔡惠雯 Tsai, Hui-Wen 柯明道 Ker, Ming-Dou 電子工程學系 電子研究所 |
| 關鍵字: | 栓鎖;防護環;過度電性應力;靜電防護元件;latchup;guard ring;EOS;ESD device |
| 公開日期: | 2015 |
| URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079811823 http://hdl.handle.net/11536/125926 |
| 顯示於類別： | 畢業論文 |
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
- 佈局最佳化的低壓元件堆疊來達成高壓積體電路之靜電放電防護設計 / 廖顯峰;Liao, Seian-Feng;柯明道;Ker, Ming-Dou
- Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process / Hsu, Sheng-Fu;Ker, Ming-Dou;Lin, Geeng-Lih;Jou, Yeh-Ning
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product / Lin, IC;Huang, CY;Chao, CJ;Ker, MD
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