標題: 5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
作者: Hsiao, Yu-Chih
Meng, Chinchun
Syu, Jin-Siang
Lin, Chung-Yo
Wong, Shyh-Chyi
Huang, Guo-Wei
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: low power;direct-conversion receiver;vertical-NPN bipolar junction transistor
公開日期: 1-Jan-2012
摘要: This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.
URI: http://hdl.handle.net/11536/150603
期刊: 2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)
起始頁: 301
結束頁: 304
Appears in Collections:Conferences Paper