標題: | Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-mu m CMOS Process |
作者: | Chen, Chun-Cheng Ker, Ming-Dou 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | latch-up;guard ring;design rule;holding voltage |
公開日期: | 1-一月-2019 |
摘要: | This work studied the latch-up path between two PMOS devices powered by different supply voltages in a 0.18- m CMOS process. In IC field applications, such a non-typical latch up path between two PMOS devices was ever fired to cause unrecoverable failures. Through the silicon test chip, the latch-up path between I/O PMOS and core PMOS was investigated in details. The measurement results from the silicon chip with split test structures can be used to investigate the design rules on anode-to-cathode spacing and guard ring placement to prevent such PMOS-to-PMOS latch-up issue. In chip layout of IC products, the PMOS devices in different power domains shall be carefully checked to prevent the occurrence of such unexpected latch-up path. |
URI: | http://hdl.handle.net/11536/152120 |
ISBN: | 978-1-5386-9504-3 |
ISSN: | 1541-7026 |
期刊: | 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) |
起始頁: | 0 |
結束頁: | 0 |
顯示於類別: | 會議論文 |