完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTsai, Yi-Chiehen_US
dc.contributor.authorHu, Han-Wenen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2020-10-05T02:01:09Z-
dc.date.available2020-10-05T02:01:09Z-
dc.date.issued2020-08-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2020.3001163en_US
dc.identifier.urihttp://hdl.handle.net/11536/155190-
dc.description.abstractLow-thermal-budget (180 degrees C for 15 sec) Cu pillar to Cu pillar bonding with Pd passivation under the atmosphere is developed without any planarization pretreatment before the bonding process. The bonded structure is investigated with material analysis, electrical measurement and reliability test. The results show that although the Cu pillar has a high roughness surface due to the electroplating process with a high deposition rate, Cu atoms can still diffuse and connect through the passivation layer and perform the low-thermal-budget Cu pillar direct bonding. Low specific contact resistance and stable resistance of daisy chain shown in the reliability test reveal the excellent bonding quality and integrity. This Cu-Cu bonding method is therefore favorable for chip stacking technology development in 3D packaging domain.en_US
dc.language.isoen_USen_US
dc.subjectThree-dimensional integrationen_US
dc.subjectCu-Cu bondingen_US
dc.subjectchip stackingen_US
dc.titleLow Temperature Copper-Copper Bonding of Non-Planarized Copper Pillar With Passivationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2020.3001163en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume41en_US
dc.citation.issue8en_US
dc.citation.spage1229en_US
dc.citation.epage1232en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000552970000020en_US
dc.citation.woscount0en_US
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