標題: A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
作者: Lee, Yuan-Sheng
Ho, Wei-Hsiang
Chen, Wei-Zen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Baud rate CDR;demultiplexer;integrating-type receiver;jitter tolerance (JTOL);optical receiver
公開日期: 1-Aug-2019
摘要: This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2(31)-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm(2). The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
URI: http://dx.doi.org/10.1109/JSSC.2019.2907804
http://hdl.handle.net/11536/155407
ISSN: 0018-9200
DOI: 10.1109/JSSC.2019.2907804
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 54
Issue: 8
起始頁: 2243
結束頁: 2254
Appears in Collections:Articles