An efficient design-for-verification technique for HDLs

Abstract

Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process. There is an emerging need for a practical solution to reduce the verification time. In manufacturing test, a well-known technique, "design-for-testability'', is often used to reduce the testing time. By inserting some extra circuits on the hard-to-test points, the testability can be improved and the testing time can be reduced. In this paper, we apply the similar idea to functional verification and propose an efficient "design-for-verification" (DFV) technique to help users reduce the verification time. The conditions for hard-to-control (HTC) codes in a HDL design are clearly defined, and an efficient algorithm to detect them automatically is proposed. Besides the HTC detection, we also propose an algorithm that can eliminate those HTC points with minimum number of DFV points. By the help of those DFV points, the number of required test patterns to reach the same coverage can be greatly reduced especially for deep-sequential designs.