Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection

doi:10.1109/TDMR.2014.2311130

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, Chun-Yu	en_US
dc.contributor.author	Fan, Mei-Lian	en_US
dc.date.accessioned	2014-12-08T15:36:21Z	-
dc.date.available	2014-12-08T15:36:21Z	-
dc.date.issued	2014-06-01	en_US
dc.identifier.issn	1530-4388	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TDMR.2014.2311130	en_US
dc.identifier.uri	http://hdl.handle.net/11536/24688	-
dc.description.abstract	The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.	en_US
dc.language.iso	en_US	en_US
dc.subject	Diode	en_US
dc.subject	electrostatic discharge (ESD)	en_US
dc.subject	layout	en_US
dc.subject	stackup	en_US
dc.title	Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TDMR.2014.2311130	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY	en_US
dc.citation.volume	14	en_US
dc.citation.issue	2	en_US
dc.citation.spage	775	en_US
dc.citation.epage	777	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000337132200027	-
dc.citation.woscount	1	-
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