高壓製程積體電路之靜電放電防護設計與應用

Abstract

高壓製程積體電路在車用電子，消費性電子產品，以及驅動電路等方面，近年來均獲得極大的重視與廣泛應用。在電子系統中，靜電放電防護能力為產品可靠度的重要指標之一。在高壓製程中，由於複雜的元件結構，其靜電放電防護設計，具有相當之困難度及挑戰。 N型橫向雙擴散金氧半電晶體 (n-channel lateral DMOS)普遍具有不佳之靜電放電防護能力；為了提升該元件之靜電放電防護能力，一具格子形狀 (waffle)之特殊佈局方式於章節二中提出。該佈局方式可使元件保存其電流驅動能力，並於對角線上得到額外之觸發點；透過該額外觸發點，N型橫向雙擴散金氧半電晶體得以透過基極觸發之技巧，來促進靜電放電發生時，元件之均勻導通程度，以提升其靜電放電防護能力。該佈局成效已於一0.5微米及一0.35微米高壓製程中獲得實際驗證。 使用矽控整流器為在高壓製程中提升靜電放電防護能力的解決方案之一。然而，矽控整流器在實際應用中，會造成其他可靠度疑慮，例如元件之安全操作區間(Safe Operating Area)受到壓縮。在章節三中，首先針對安全操作區間及目前習知的改進技術，做一詳細的介紹。於章節四中，則特別提出一多晶矽閘極彎曲之特殊元件佈局方式，以改善因使用矽控整流器在N型橫向雙擴散金氧半電晶體中，對安全操作區間所造成的負面影響。 除兩種元件等級的新型佈局方式外，由於積體電路產品需要達到靜電放電防護能力的規格要求，本論文分別於章節五及章節六，提出兩個已成功應用於商用積體電路產品的創新靜電放電防護設計。此兩個靜電放電防護設計，皆應用於全金屬矽化物製程(fully-silicided)之積體電路產品。使用全金屬矽化物製程可提升積體電路產品的電路性能，但卻會造成靜電放電防護能力的下降。特殊的靜電放電防護設計，為全金屬矽化物製程中的必要設計。章節五中，透過兩種鎮流電阻(ballast resistance)設計方式，順利將一款微控制積體電路晶片之人體靜電放電模式靜電放電防護能力，由1.5千伏特提升至超過6千伏特。 章節六的全金屬矽化物製程靜電放電防護設計，為專為電壓程式腳位應用所做出的創新設計。在記憶體寫入時，該電壓程式腳位將升壓至一大於正常工作電壓之電位。因此，該腳位之靜電放電防護設計，需符合開汲極與故障保險(open drain / fail safe)的設計需求：自電壓程式腳位至電源線間，不能有順偏二極體的存在，以避免漏電流的產生。此外，該靜電放電防護設計，在電壓程式訊號具備極快速的電壓上升時間(數十奈秒等級)下，仍可避免誤觸發的問題，不影響記憶體寫入的操作。此一特性，使得具備該靜電放電防護設計的微控制器，可通用市面上多種記憶體寫入器。本靜電放電防護設計，已於一矽晶片上實際驗證，可提供五千伏特之人體靜電放電防護耐受度。 在廣泛的可靠度議題中，除靜電放電防護設計外，閂鎖效應為另一個重要的設計考量。在考量閂鎖效應時，元件之維持電壓(holding voltage)為一重要的參考指標。章節七則探討N型橫向雙擴散金氧半電晶體，其維持電壓對時間的關聯性。透過長脈寬傳輸線觸波產生系統的量測，發現N型橫向雙擴散金氧半電晶體的維持電壓，會隨著時間的經過而下降。該現象將造成未來高壓製程中閂鎖效應的測試方式與佈局準則訂定的不同考量。 簡而言之，本論文提出創新的學術研究貢獻，更針對實際積體電路產品之靜電放電防護，做出切題且創新的實用設計。本論文促進了解高壓製程中元件於靜電放電時的反應與現象，並提供數種於高壓積體電路製程中可實用的靜電放電防護解決方案。

High-voltage (HV) technologies are booming in recent years due to the increasing demand on automotive electronics, consumer integrated circuits (ICs), driver circuits for display panels and so forth. To have a rigorous end product or electronic system, electrostatic discharge (ESD) is one of the most important factors affecting IC reliabilities; IC industries are struggling for good ESD protection designs due to the structural complexity of transistors and application varieties in HV technologies. The n-channel lateral DMOS (nLDMOS) devices in HV technologies are known to have poor ESD robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed in chapter 2 to fulfill the body current injection technique. The proposed layout and circuit co-design method on high-voltage nLDMOS has been successfully verified in a 0.5-□m 16-V BCD process and a 0.35-□m 24-V BCD process without using additional process modification. Experimental results have shown significantly improved turn-on uniformity and ESD robustness of nLDMOS. Silicon controlled rectifier (SCR) in HV technologies is usually embedded in output arrays to provide a robust and self-protected ESD capability. Though the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mis-triggering of the embedded SCR during normal circuit operating conditions can bring other application reliability concerns. The safe operating area (SOA) of output arrays due to SCR insertion has seldom been evaluated. In chapter 3, SOA is first reviewed and in chapter 4, the impact of embedding SCR to the electrical SOA (eSOA) of an nLDMOS array is investigated. Experimental results showed the nLDMOS array suffers substantial degradation on eSOA due to the embedded SCR. Design approaches, including a new proposed poly bending layout, is proposed in chapter 4. With the poly bending layout method, both high ESD robustness and a wide SOA can be achieved at the same time on an nLDMOS output array. In addition to the two layout designs in Chapter 2 and 4, another two practical fully-silicided designs have been applied to IC products and have passed product-level ESD verifications. Silicidation is a common process step which can improve the circuit operating speed but has been reported to substantially decrease ESD robustness of MOSFETs. Silicide blocking is a useful method to alleviate this ESD degradation from silicidation, but it requires additional mask and process steps and the fabrication cost is increased. For cost reduction, two new ballasting layout schemes are included in chapter 5 to effectively improve ESD robustness of fully-silicided push-pull I/O buffers without using the silicide blocking. Results from real IC products have confirmed that the new ballasting layout schemes can successfully increase human-body model (HBM) ESD robustness of fully-silicided I/O buffers from 1.5 to over 6 kV. The other fully-silicided ESD protection design in chapter 6 is for ICs with a voltage programming (VPP) pin. When programming read only memories (ROM), a voltage higher than the normal power supply voltage (VDD) is applied to the VPP pin. A fail-safe structure that does not have a diode current path to VDD power supply line is necessary for a VPP pin. A new VPP pin ESD protection design is necessary for the fully-silicided and the fail-safe requirements. The design proposed in chapter 6 not only meets the two requirements but also features high resistivity to mis-triggering when the VPP programming voltage has a fast rise time. This special design consideration makes ICs with the ESD protection design be compatible to ROM programmers that can have fast voltage slew rate on VPP pins when programming. This new VPP pin ESD protection design has been successfully verified on a commercial IC product and equipped the IC with an HBM ESD protection level of 5 kV. Besides the requirement of high ESD robustness, latchup is another important reliability consideration for silicon ICs, especially in HV technologies. Holding voltage is one of the critical design considerations when developing elements with high latchup immunity. Because a HV device is easily damaged by the huge power generated from direct current (DC) curve tracer, the device holding voltage with respect to latchup immunity is often referred to the holding voltage measured by TLP systems with a 100-ns pulse width. To evaluate the validity of this practice, a long-pulse TLP system were used to investigate characteristics of an nLDMOS’s holding voltage in time domain. Measurement results in chapter 7 revealed that the self-heating effect results in overestimation of the holding voltage acquired from a 100-ns TLP system. A gradually decreasing holding voltage of the nLDMOS in time domain is observed, which leads to new concerns when engineering holding voltage of transistors in HV technologies. With these novel results in HV technologies, this dissertation provides both advanced academia research achievements and practical ESD design solutions to IC industries.