具不同應力及高介電層金氧半場效電晶體之可靠度研究

Abstract

本論文主要探討的是，以聚應力接觸孔蝕刻停止層之二氧化鉿為基底之高介電常數閘極介電層中的電荷捕捉與逃逸之各種不同的電特性分析。與傳統的二氧化矽(SiO2)或氮氧化矽(SiON)閘極氧化層不同的是，以二氧化鉿為基底之高介電常數閘極介電層具有相當嚴重的可靠度問題—臨界電壓的不穩定性，起因於早已存在的主體缺陷中的快速與緩慢的電荷捕捉與逃逸現象，特別是對於處在矽基底電子注射狀態下的N 型金氧半場效電晶體而言。我們發現，在偏壓高溫不穩定性(bias-temperature instability, BTI)應力測試的應力/量測循環之中，這些被捕捉的電荷載子將導致半導體元件中臨界電壓的偏移、汲極電流的衰減，以及通道載子移動率的變異。同時我們也改變不同偏壓電壓、偏壓時間、偏壓溫度…等，對這些被捕捉的電荷載子將導致半導體元件中臨界電壓的偏移、汲極電流的衰減，以及通道載子移動率的變異作更深入的探討，同時我們也做Channel Hot Carrier stress的量測和探討，來了解在Channel Hot Carrier stress下，以聚應力接觸孔蝕刻停止層之二氧化鉿為基底之高介電常數閘極介電層中的電荷捕捉與逃逸之各種不同的電特性分析。同時我們也使用Pulse IV 來進行直流電性和可靠度量測的探討，藉此將fast transient charge effect的效應做出分析和探討

This dissertation majorly studies the charge trapping and de-trapping in Hf-based high-k gate dielectrics with different contacting etching stopping layer thickness through various electrical characterizations under changing different stress condition. Unlike the conventional SiO2 or SiON gate oxides, Hf-based high-k gate dielectrics are known to suffer from the serious reliability concern of threshold voltage instability due to the fast and slow charge trapping and de-trapping in the pre-existing bulk traps in Hf-based high-k gate dielectric, especially under the substrate electron injection conditions in high-k NMOSFETs. However, these trapped charge carriers are believed to cause the threshold voltage shift, drain current degradation, and channel mobility variation during the stress/measure cycles of bias temperature instability (BTI) stress. In the meantime, we still carry out hot carrier stress for studying the charge trapping and de-trapping in Hf-based high-k gate dielectric with different contacting etching stopping layer thickness through various electrical characterizations under changing different stress condition. We also utilize pulse iv to measurement and analyze the performance and reliability compared with DC measurement.