H.264 Baseline 解碼器電路設計

Abstract

本論文主旨在於Leon平台上建構H.264 硬體解碼器，透過AMBA bus Protocol，將H.264檔案從SDRAM搬運到硬體解碼器進行解碼，解碼完成的影片再透過Burst Mode將解碼完成的影像回傳。本論文主要在講述如何實作各個H.264重要元件的方法，以及各個元件之間的同步，每個元件因所需要消耗bitstream bits數不同，正確的將bitstream放到合適的元件中作解碼，並對於各個部分所需要用到的block ram作一些說明及使用，利用Leon平台驗證設計電路的正確性。本論文完整的實作baseline各個元件CAVLC、Inter prediction、Intra prediction、IQIT和一些發出同步訊號的狀態機。

In this thesis, we present the design of an H.264 Hardware Decoder IP for a Leon embedded processor platform. The functional behavior of the IP is as follows. The bus master IP will read the input H.264 bitstream from SDRAM using AMBA AHB protocol, decode the bitstream in real-time, and write the decoded frames back to SDRAM using burst transfer mode. The whole process is performed without intervention from the Leon processor core. This paper presents the design and implementation of every key components of an H.264 baseline decoder. Because different decoder components consume different amount of bits along their operations, it is not trivial to perform synchronization among hardware components. Therefore, the controllers used to synchronize the operations will be discussed. In addition, the use of on-chip memory in every part of the design would be illustrated in detail. Finally, we verify the correctness of the designed circuits on a Leon soft-core processor platform. In summary, the H.264 components including high-level syntax parser, CAVLC, inter prediction, intra Prediction, IQIT, and the synchronizing state machines have been completely implemented and verified.