管線式影像細線化之 FPGA 硬體設計

Abstract

影像處理中用來表示一平面區域的結構的重要方法之一是將其簡化為一曲 線圖。這種簡化可以透過取得區域的骨架(細線化)來完成。細線化因其能 有效簡化資料並增強物體特徵的萃取，此種方法被廣泛的運用於圖形識別 系統如指紋辨識、手寫字辨識系統的前處理步驟。現有的細線化處理一般 用軟體程式重來完成，我們的方法是利用一 ASIC Chip 來解決此一處理 的即時性問題。在本論文中，我們提出一個處理方二元圖形細線化的硬體 架構。此一管線式影像細線化的架構建立在一高度平行化的細線化演算法 上。此一演算法利用 3*3 型罩對物體作細線化處理。此一架構被應用於 超大型積體電路設計，對處理一張 512*512 的二元圖不超過 0.07 秒。 Skeletonizing is widely used in the preprocessing stageof pattern recognition operations, such as fingerprintidentification and OCR, to compress data and tofurthersupport feature extraction in the subsequent stage. It normally reduces a digitzed pattern to a skeleton suchthat all resulting branches are of only 1pixel thick-ness. In addition to a pure software implementation offingerprintskeletonization, our ASIC solution makesskeletonization available for a normal real- time envi-ronment. In this thesis, we propose a special purpose VLSI archi-tecture for binary image skeletonization. This pipelineddataflow architecture is based on a modified parallelskeletonizing algorithm that skeletonizes a 512*512 imagea high degree parallelism. Our algorithm is mapped ontoa single chipimplementation for skeletonizing a 512*512 binary image within about 0.07 sec.