射頻/中頻低功率除像濾波器設計

Abstract

本論文完成除像濾波器的低功率設計與實現，應用在外差的接收器。電路製程採用聯電的0.25 um CMOS製程，量測電壓為2.5伏特。 用於除像的2.4 GHz峽谷濾波器是由電感、可變電容和負電阻電路所組成。電感和可變電容提供可調變的極點和零點；負電阻電路增加濾波器的品質因素。所提出的設計能達到20dB的除像成果、30的品質因素以及小於1mA的消耗電流。整合低雜訊放大器和除像濾波器的單晶電路實現前端電路的整合。 用於除像的7.0 MHz多相濾波器是由電阻、電容和放大器電路所組成。多加的被動元件和蛇行的連線改進振幅和相位的匹配；放大器電路還原被衰減的訊號。此多相濾波器電路能達到65dB的除像成果、3 MHz的頻寬，以及沒有消耗電流。

Low power design and implementation of image-rejection filters for the heterodyne receiver had been proposed and been implemented in UMC 0.25 um CMOS technology and measured at 2.5 V. 2.4 GHz notch filter for image-rejection consists of inductors, varactors and negative-resistance circuit. The inductors and varactors provide the tunable poles and zeros; the negative-resistance circuit increases the quality factor of the filter. The proposed design achieves 20dB image rejection, quality-factor (Q) up to 30, and less than 1mA consumed current. Monolithic integration of LNA and IRF had also been implemented for front-end integration. 7.0 MHz poly-phase filter for image-rejection consists of resistances, capacitors and amplifier circuit. The dummy of passive components and snake interconnection improve the amplitude and phase matching; the amplifier circuit compensates the attenuated signals. The proposed design achieves 65dB image rejection, bandwidth up to 3 MHz, and with no consumed current.