高效率無線腦波監測前端系統晶片設計 及其於即時腦機介面的應用

Abstract

近年來老年人口比例快速增加，全球年齡超過六十五歲以上的人口預計在2025年會達到7.61億人口。這樣會使社會邁入老年化且會造成醫療照顧等相關問題。因此整合型可攜式照護系統的相關研究成為已經成為近年來的重要課題。 本論文為針對腦電訊號 (EEG)所發展出之可攜式低功耗無線擷取系統，系統中包括一具延展性的單通道類比前端晶片，以及一微控器和藍芽2.0傳輸模組。本系統以應用於加護病房的整合型可攜式醫療照護系統為目標發展，由於傳統腦波擷取儀器十分龐大以及笨重，本論文亦致力於腦波監測系統的微小和輕量化。 由於腦電訊號十分微弱，為了使其可以正常被觀察及應用，因此在系統設計上必須準確且不失真地放大腦電訊號。此微弱的腦電訊號相當容易受外在雜訊干擾，因此在設計上，必須有效減少雜訊造成的影響，此為單通道類比前端晶片所設計之核心概念。此外為使用數位晶片來處理腦電訊號或是使用腦電訊號來做人機介面的應用，單通道類比前端晶片也內建有一10位元的類比/數位轉換器。 而要把數個不同的晶片整合在一個系統裡，其中晶片間的電壓準位，訊號的溝通都是重要的課題。 本論文中之單通道類比前端晶片使用Chopper Different Difference Amplifier做為儀表放大器，再經加強放大級和低通濾波器來放大信號和取出腦波頻段。而此單通道類比前端晶片使用了除頻器來變換時脈周期;使得類比/數位轉換器和並列/串列轉換介面工作在不同的速度，藉以達到可延伸通道數的功能。 最後，本論文所使用單通道類比前端晶片已被設計並透過台積電180奈米製程下線並完成測試。

Proportion aging is increasing rapidly in recent years. The worldwide population of people over the age of 65 has been predicted to become 761 million in this year 2025. Hence, the aging society will have a great demand of the healthcare system for elders, especially an integrated portable one. This thesis is a power-efficient and wireless EEG front-end system that focused on electroencephalogram (EEG) signal. In this system, an extendable single channel analog front-end chip, a micro-controller and a Bluetooth 2.0 module is included. This is an integrated health care system with portability that committed to the Intensive Care Unit (ICU). This system can also apply to Brain-Computer Interface (BCI). Since traditional EEG front-end equipment is very large and bulky, this work also devotes on small and light-weight of the EEG monitoring system. Because of the weakness of EEG signals, it is necessary to amplify it for accurate monitoring. EEG signal is easily affected by external noise and artifact, so the single channel analog front-end chip is mainly designed for erasing noise. In other hand, for the purpose of digital signal processing or Brain-Computer interface (BCI), the chip also has a built-in analog-to-digital converter (ADC). There are several important issues to integrate multiple chips into a system such as voltage level and communication between different chips. The single channel analog front-end chip presenting in this thesis has used Chopper Different Difference Amplifier (CHDDA) as instrument amplifier, negative feedback amplifier to amplify the EEG signal and low-pass filter to filter the frequency region that needed. The divider is designed to make ADC and serial/parallel interface (SPI) operating at different clock rate, so that the number of channels can be extended.