應用於低功率事件驅動感知平台之超低電壓全數位操控線性穩壓器

Abstract

在本篇論文中，我們提出了兩種應用於低功率事件驅動感知平台的全數位操控線性穩壓器。兩個全數位操控線性穩壓器皆實現在台積電65奈米低功耗CMOS製程，並可運作在近臨界操作電壓。 在第一個全數位操控線性穩壓器中，使用數位錯誤偵測器取代類比放大器。一種新的製程、電壓、溫度感知設計用來減輕環境變異，並提升全數位操控線性穩壓器的解析度。 在第二個全數位操控線性穩壓器中，使用以比較器為基礎的錯誤偵測器取代類比放大器。在不同的環境變異與負載變化下，我們提出兩種方法來調整PMOS的強度，以達到降低輸出漣漪的目的。

In this thesis, two digitally controlled linear voltage regulators are proposed for event-driven energy-efficiency sensing platform. Both digitally controlled linear voltage regulators are implemented on TSMC 65-nm low-power bulk CMOS technology and designed for near-/sub- threshold operations. The first digitally controlled linear voltage regulator includes a digital error detector (DED), which is the replacement of the analog error amplifier. A novel Process-Voltage-Temperature (PVT) –aware design is implemented to mitigate environmental variations and to guarantee the resolution of linear voltage regulator. In the second digitally controlled linear voltage regulator, a comparator-based error detector is proposed to replace analog error amplifier. Two methods are introduced to reduce self-generated output ripple by adjusting the PMOS strength for PVT and load variations.