全數位鎖相迴路設計與應用之研究(III)

標題:	全數位鎖相迴路設計與應用之研究(III) The Study of all Digital Phase Lock Loop Design and Its Applications(III)
作者:	李鎮宜 LEE CHEN-YI 交通大學電子工程系
關鍵字:	鎖相迴路;電路設計;振盪電路;Phase lock loop (PLL);Circuit design;oscillation circuit
公開日期:	2001
官方說明文件#:	NSC90-2215-E009-105
URI:	http://hdl.handle.net/11536/93384 https://www.grb.gov.tw/search/planDetail?id=665804&docId=126399
Appears in Collections:	Research Plans

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