電路中間聯結的模式簡化:基於平衡實現的方法

Full metadata record

DC Field	Value	Language
dc.contributor.author	林清安	en_US
dc.contributor.author	LIN CHING-AN	en_US
dc.date.accessioned	2014-12-13T10:37:35Z	-
dc.date.available	2014-12-13T10:37:35Z	-
dc.date.issued	2001	en_US
dc.identifier.govdoc	NSC90-2215-E009-055	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94743	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=665658&docId=126362	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	電路模式	zh_TW
dc.subject	平衡實現	zh_TW
dc.subject	電路連接	zh_TW
dc.subject	積體電路設計	zh_TW
dc.subject	Circuit model	en_US
dc.subject	Balanced realization	en_US
dc.subject	Circuit connection	en_US
dc.subject	Integrated circuit design	en_US
dc.title	電路中間聯結的模式簡化:基於平衡實現的方法	zh_TW
dc.title	Circuit Interconnect Model Reduction : A Balanced Realization Based Approach	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電機與控制工程系	zh_TW
Appears in Collections:	Research Plans

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