A shift register architecture for high-speed data sorting

Abstract

This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1) shift right, (2) shift left, (3) load, and (4) initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells, sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2 mu m CMOS double-metal technology.