A 17-nW, 0.5V, 500S/s, Rail-to-Rail SAR ADC with 8.1 Effective Number of Bits

Abstract

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 mu m CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.