A 5.15-5.825 GHz high-gain and low-noise CMOS down-conversion mixer with low-power for WLAN 802.11a

Abstract

This paper presents a 5.15GHz-5.825GHz CMOS down-conversion mixer with high-gain, low-noise, and low-power for WLAN 802.11a receiver. The cascade topology is adopted at the transconductance stage to improve power gain and reduce noise factor. And the inductive peaking technique is implemented at the switching stage to flatten the frequency bandwidth of conversion gain. This mixer is implemented in TSMC 0.18 mu m CMOS process, and the chip size including the test pads is 1.2mm(2). The proposed mixer offers a measured conversion gain from 26.2 to 26.7dB, a flat DSB noise figure from 7.3 to 8dB with IF 10MHz, and input third-order intercept point from 8 to -12dBm, over the whole working range, while consuming 11.32mW from a 1.8V supply voltage.