Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs

Abstract

For integrated circuits (ICs) with voltage programming pin (V(PP) pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V(PP) pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to V(DD) cannot be applied to such V(PP) pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V(PP) pin with the consideration of the mistriggering issue when V(PP) programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.