Adaptive Power Control Technique on Power-Gated Circuitries

Abstract

An adaptive power control (APC) system on power-gated circuitries is proposed. The core technique is a switching state determination mechanism as an alternative of critical path replicas. It is intrinsically tolerant of process, voltage, and temperature (PVT) variations because it directly monitors the behavior of VDDV node. The APC system includes a multi-mode power gating network, a voltage sensor, a variable threshold comparator, a slack detection block, and a bank of bidirectional shift registers. By dynamically configuring the size of power gating devices, an average of 56.5% unused slack resulted from worst case margins or input pattern change can be further utilized. A 32-64 bit multiply-accumulate (MAC) unit is fabricated using UMC 90-nm standard process CMOS technology as a test vehicle. The measurement results of test chips exhibit an average of 12.39% net power reduction. A 7.96 x leakage reduction is reported by power gating the MAC unit. For the 32-bit multiplier of MAC, the area and power overhead of proposed APC system are 5% and 1.08%, respectively. Most of the overhead is contributed by power gating devices and their control signal buffers.