Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices

Abstract

In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. In the hybrid design, TFETs are used for the top critical path to reduce the longest path delay, and FinFETs are used for the rest of the circuit to reduce switching power and leakage power. The PDP of the hybrid TFET-FinFET CLA circuit is better than the circuits with all FinFET and all TFET implementations in the vicinity of V-DD=0.3V. However, as the operating voltage is further reduced, the lower-ranked critical paths (e.g. 2nd critical path) with some FinFET devices in the path stick out, and the delay and PDP become inferior to all TFET implementation.