Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration

Abstract

In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270 degrees C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn mu-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 mu m bump pitch, 40 mu m diameter of Cu/Sn mu-bump and 50 mu m diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.