The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs

Abstract

The impact of channel width scaling on low-frequency noise (LFN) and high-frequency performance in multifinger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-induced Delta W is identified as an important factor that is responsible for the increase in transconductance G(m) and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mobility (mu(eff)) degradation from STI stress and the increase in effective width (W(eff)) from Delta W due to STI TCR. The proposed model can accurately predict width scaling effect on G(m) based on a tradeoff between mu(eff) and W(eff). The enhanced STI stress may lead to an increase in interface traps density (N(it)), but the influence is relatively minor and can be compensated by the W(eff) effect. Unfortunately, the extremely narrow devices suffer f(T) degradation due to an increase in C(gg). The investigation of impact from width scaling on mu(eff), G(m), and LFN, as well as the tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.