A systematic approach for low phase noise CMOS VCO design

Abstract

The fully integrated LC voltage controlled oscillator by 0.35 mum CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is. attained. The phase noise of measured value which shows good match with calculating data is about -115.5dBc/Hz at off set frequency 600 kHz.