Fast-locked clock and data recovery circuit and the method thereof

Abstract

The present invention discloses a fast-locked clock and data recovery circuit, which adopts a 2× oversampling technology and comprises: a multi phase-outputting phase-locked loop generating a plurality of phases θi; a phase interpolator synthesizing the obtained phases θn and θn+2 into a sampling phase Φn based on the weighting coefficient k; a phase detector detects the phase lead or lag between the input data and the sampling phase and generates an up/down signal; and a phase search engine update the weighting coefficient and modulate the sampling phase according to the up/down correction signals. Further, the present invention proposes a data recovery circuit implementing a binary search method and a 2× oversampling method, whereby the time for clock locking can be greatly reduced. Furthermore, the present invention utilizes a multi-phase time-sharing parallel sampling technology to achieve high-speed operation and low power consumption.