Cost-Efficiency FFT Using Hardware-Reduction and Dynamic Current Scaling Approaches

Abstract

In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.