Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Application

Abstract

'Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS are employed and the capacitance mismatch due to process variation is compensated using a self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm(2). The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step.