A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18-mu m 1.8-V/3.3-V Low-Voltage CMOS Process

Abstract

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-mu m 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pullup switch to withstand 4 times the nominal supply voltage (4 x VDD). With the dc input voltage of 3.3 V, the regulated threestage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pulldown current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm(2) for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.