Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

Abstract

The correlation between channel mobility gain (Delta mu), linear drain-current gain (AIdlin), and saturation draincurrent gain (Delta I-dsat) of nanoscale strained CMOSFETs are reported. From the plots of Delta I-dlin versus Delta I-dsat and ballistic efficiency (B-sat,B-PSS), the ratio of source/drain parasitic resistance (R-sat,R-PSS) to channel resistance (R-CH,R-PSS) of strained CMOSFETs can be extracted. By plotting Delta mu versus Delta I-dlin, the efficiency of Delta mu translated to Delta I-dlin is higher for strained pMOSFETs than strained nMOSFETs due to smaller R-SD,R-PSS-to-R-CH,R-PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the R-SD,R-PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the Delta I-dli -to-Delta mu sensitivity is maintained until R-SD,R-PSS becomes comparable to/or higher than R-CH,R-PSS.