Efficient improvement of hot-carrier-induced device's degradation for sub-0.1 mu m complementary metal-oxide-semiconductor field-effect-transistor technology

Abstract

The effect of post-thermal annealing (PA) after In-halo and As-halo implantation on the reliability of sub-0.1 mum complementary metal-oxide-semiconductor field-effect-transistors was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced device's degradation. The optimal results of device performance as well as of reliability can be obtained with post-annealing treatment performed at medium temperatures (e.g.. 900degreesC) for a longer time.