A high throughput variable length decoder with modified memory based architecture

Abstract

Variable-Length Code (VLC) is the most popular data compression technique. Therefore, a high throughput Variable-Length Decoder (VLD) is required in many applications. In this paper, we propose 2 simple modified methods which can increase throughput of memory-based two-bit structure Variable-Length Decoder system [1]*. The additional hardware of modified architecture is some control unit and a little memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6um CMOS process and MPEG2 coding table-15 can achieve 720M bits/s with 100MHz clock rate.