An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices

Abstract

In this paper, an improved gate-diode technique has been developed for the interface characterization on both n- and p-MOSFET's with gate oxide in the direct tunneling regime. This method has been demonstrated successfully for measuring oxide damage in all of the channel, space-charge (or junction), and drain extension regions in 20Angstrom ultra-thin gate oxide devices. As an application of the present method, the lateral profile of localized oxide damage due to Negative Bias Temperature Instability (NBTI) or Hot Carrier (HC) effect has been demonstrated. It provides us an understanding of the correlation between the device degradation and various stress-induced oxide damage in CMOS devices.