A 723-MHz 17.2-mW CMOS programmable counter - Chang, HH; Wu, JC (My University, 1998)
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.
Keywords: CMOS digital integrated circuits; flip-flop circuits; logic design; phase-locked loops; programmable circuits