A hardware-efficient architecture for 3-D graphics processor - Liang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G (My University, 1995)
In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.