High load driving device - Chuang Ching-Te; Lu Chien-Yu (My University, 2011)
A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.