| Title: | 後次微米時代新興電子設計自動化技術之研究---子計畫三：角落錯誤之矽除錯(II) Silicon Debug for Hard-Corner Design Errors(II) |
| Authors: | 周景揚 JOU JING-YANG 國立交通大學電子工程學系及電子研究所 |
| Issue Date: | 2009 |
| Gov't Doc #: | NSC98-2220-E009-023 |
| URI: | http://hdl.handle.net/11536/101427 https://www.grb.gov.tw/search/planDetail?id=1901318&docId=314960 |
| Appears in Collections: | Research Plans |
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