Title: 穿隧場效電晶體及混合穿隧場效電晶體與金氧半場效電晶體的邏輯電路與靜態隨機存取記憶體之探索與評估
Exploration and Evaluation of Tunneling FET (TFET)-Based and Mixed TFET-MOSFET Logic Circuits and SRAMs
Authors: 莊景德
Chuang Ching-Te
國立交通大學電子工程學系及電子研究所
Issue Date: 2014
Gov't Doc #: MOST103-2221-E009-196-MY2
URI: http://hdl.handle.net/11536/102466
https://www.grb.gov.tw/search/planDetail?id=8363449&docId=449402
Appears in Collections:Research Plans