後次微米時代新興電子設計自動化技術之研究----子計畫二：整合性低耗電管理之技術開發(I)

Abstract

由於時脈頻率以及功能需求不斷的攀升，但是從製程演進中對耗電所能得到的好處卻趨於緩和，甚至漸漸出現了負面效應，以致於耗電密度與日俱增。根據2006年更新的ITRS所預估：耗電的問題從2007年開始變成不可不解的困擾，到了2017年會變得更加嚴重。 此外，低耗電的需求不僅是為了隨身攜帶和需要電池的裝置延長電池的持續使用時間與壽命；對於固定的常置設備，也應考慮封裝以及冷卻的成本，若是家用的電器更應考慮靜音與環保。 低耗電的研究雖已行之有年，但是之前的研究大多是分層級／分階段考慮，缺乏通盤的整合，導致在前期作好的最佳化結果無法在後期好好的利用。在本子計畫中，我們將提出一個整合性的低耗電管理的設計流程，開發其所需的新興技術。我們分成架構，設計，與實現，三層級探討：在架構上，我們依據所訂的低耗電規格與可利用之低耗電管理技術訂定所需的耗電架構，包含所需的耗電狀態與切換機制；在設計時，將RTL與詳細的耗電格式描繪出來；在實現階段，合成／布局／擺置／繞線的時候，考慮所訂定的耗電狀態，對耗電與其他設計考量一起最佳化。最後，當無法達成預定規格時，我們提出耗電架構的修改方向。

As the power benefits from process scaling have been slowing down, higher clock rates and more functionalities contribute to significant growth in power density. According to the ITRS 2006 power consumption trends, we are in trouble since 2007 and will get in deeper trouble after 2017. It is common to consider low power in portable and/or battery-powered devices; however, power consumption (and heat generation) is also important to stationary installations. For example, a data center electricity costs some US$3 billion annually. In addition, quieter and healthy devices are desirable at living places. Low power consumption implies low heat dissipation, which improves system stability and reduces energy use, thus saving money and reducing the burden on the environment. Although low power has drained much research attention for a long time, most of previous works focus on a certain stage without overall consideration. Hence, the optimality obtained at early stages cannot sustain to late stages. In this subproject, we will propose an integrated low power management methodology and develop its technologies. We will divide the flow into architecture, design, and implementation aspects. At the architectural stage, we will define a power architecture according to the power specifications and available power management techniques. This power architecture will be given as a power-state-machine. At the design stage, the RTL description and the detailed power format will be completed. At the implementation stage, power-aware synthesis/floorplanning/placement/routing will be performed, as well as, the implemented results will be feedback to and be used to further modify the power architecture.