Title: A multilayer data copy test data com pression scheme for reducing shifting-in power for multiple scan design
Authors: Lin, Shih-Ping
Lee, Chung-Len
Chen, Jwu-E
Chen, Ji-Jan
Luo, Kun-Lun
Wu, Wen-Ching
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: circuit testing;low-power testing;test data compression;test pattern generation
Issue Date: 1-Jul-2007
Abstract: The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works Were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes,a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.
URI: http://dx.doi.org/10.1109/TVLSI.2007.899232
http://hdl.handle.net/11536/10646
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2007.899232
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 15
Issue: 7
Begin Page: 767
End Page: 776
Appears in Collections:Articles


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