Title: A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
Authors: Wang, Yu-Jen
Cheng, Chao-Chung
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: H.2641AVC;motion estimation;video coding
Issue Date: 1-May-2007
Abstract: This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous design.
URI: http://dx.doi.org/10.1109/TCSVT.2007.894050
http://hdl.handle.net/11536/10854
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2007.894050
Journal: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 17
Issue: 5
Begin Page: 578
End Page: 583
Appears in Collections:Articles


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