Parallel pixel processing using programmable gate arrays

Title:	Parallel pixel processing using programmable gate arrays
Authors:	Budgett, DM Tang, PE Sharp, JH Chatwin, CR Young, RCD Wang, RK Scott, BF 電控工程研究所 Institute of Electrical and Control Engineering
Keywords:	programmable logic devices;image processing;parallel algorithms
Issue Date:	15-Aug-1996
Abstract:	A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays, a wide range of image processing algorithms can be implemented in realtime.
URI:	http://hdl.handle.net/11536/1105
ISSN:	0013-5194
Journal:	ELECTRONICS LETTERS
Volume:	32
Issue:	17
Begin Page:	1557
End Page:	1559
Appears in Collections:	Articles

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