Title: iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
Authors: Lee, Pei-Yu
Jiang, Iris Hui-Ru
Li, Cheng-Ruei
Chiu, Wei-Lun
Yang, Yu-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: static timing analysis;common path pessimism removal;engineering change order;incremental timing analysis
Issue Date: 1-Jan-2015
Abstract: To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.
URI: http://hdl.handle.net/11536/129823
ISBN: 978-1-4673-8388-2
ISSN: 1933-7760
Journal: 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)
Begin Page: 890
End Page: 894
Appears in Collections:Conferences Paper