鍺電晶體之費米能階鎖定及介面反應的探討與改進

Abstract

目前積體電路最大的挑戰，在於如何降低「場效電晶體」的工作電壓與功率消耗。 而使用高「等效速度」(effective velocity, veff)或「遷移率」(mobility)之材料來取代矽， 乃為必需的方法。於眾多材料中，鍺具有最佳的電洞「遷移率」，亦具有高的電子「遷 移率」，而形成「互補式場效電晶體」。然而鍺n 型電晶體遠較三五族電晶體困難，其主 要的原因乃為「費米能階針定至價帶」(Fermi-level pinning to Valance Band)。此效應造 成了n 型電晶體接觸電阻的增加，而降低了電晶體「驅動電流」，且隨著電晶體的微縮、 接觸面積的縮小，而愈加困難。此效應產生的另一問題則在於增加了電晶體的「起始電 壓」(Vt)，然而低的「起始電壓」乃為降低功率消耗之所必需的條件。此外，「高介電閘 極」(high-κ gate dielectric)與鍺在低溫即開始產生「介面反應」，亦造成電晶體「驅動電 流」的衰減。 本計畫即是針對以上挑戰提出解決之道。在「費米能階針定至價帶」的問題上，我 們將探討此效應產生的物理機制，並使用先進製程及｢低功函數｣金屬來降低此效應。我 們並將使用高濃度離子佈離及奈秒級｢雷射退火｣來降低接觸電阻。此奈秒級雷射亦會用 於「高介電閘極氧化層」，以改善其「介面反應」，而增加電晶體的｢驅動電流｣。此外， 我們將使用「氧化鑭」(La2O3)「高介電閘極氧化層」，以降低因「費米能階針定」所造 成的「起始電壓」增加之問題。本計畫如能成功，將對降低「積體電路」的功率消耗， 做出重大貢獻。

The lowering power consumption becomes the most important technology trend for ICs, which is especially important for mobile communication devices. However, the low power operation is a difficult challenge for CMOS ICs. To lower the DC power consumption, metal-gate and high-κ technology were implanted in Si CMOS manufacture after near a decade long R&D. To further lower the power consumption, the low voltage operation is necessary due to the fundamental physics of CiVD 2f/2; here the Ci, VD and f are the inversion capacitance, drain voltage, and operation frequency, respectively. This switching power is already higher than DC power consumption in advanced metal-gate/high-κ/Si CMOS ICs, which will become even worse as continuously increasing f and Ci during scaling. To reach the low VD operation and preserve high performance, high mobility new channel materials must be used to replace Si since the transistor drive current Id/W = Cinvveff(Vg- Vt). Here the veff is the effective velocity that is related to mobility. The Ge pMOSFET is known to be the best candidate for low VD operation due to its higher veff. However, the Ge nMOSFET is very challenging due to the limitation of reported phenomenon: Fermi-level pinning to valance band (EV). Such effect leads to poor ohmic contact to transistor, and higher transistor threshold voltage (Vt). The transistor is further degraded by the strong high-κ/Ge interface reaction and Ge out-diffusion. These issues still limit the performance of Ge nMOSFET after years long research, due to the fundamental challenges motioned above. This is the reason why Intel proposed the high mobility InGaAs to replace Ge for nMOSFET. However, the InGaAs-nMOS/Ge-pMOS architecture is very difficult due to the large 8% lattice-mismatch and anti-phase boundaries of InGaAs on Si, more complicated process steps, larger number of masks, potentially lower yield, and higher cost. Although this high performance CMOS structure is suitable for high-end product such as Intel’s microprocessor, this may not fit the low cost and high yield requirements of IC foundries. To address the Fermi-level pinning to EV and interface reaction issues, in the proposal we shall use low work-function metals to alleviate the Fermi-level pinning. The good ohmic contact RC=ρl/AC is especially important for sub-14 nm CMOS due to the smaller contact area (AC) that increases with increasing down-scaling. We shall also use high-dose As ion implantation to increase the doping concentration and lower contact resistance. In this proposal, we shall apply 30-ns laser annealing to activate implanted dopants and achieve shallow junction. To compensate the higher Vt by Fermi-level pinning to EV, we shall use La2O3 high-κ gate dielectric that has unique negative flat-band voltage (Vfb) due to polarization charge. The 30-ns laser annealing will also be applied to high-κ/Ge interface to lower the interface reaction and Ge out-diffusion. The success of this proposed work shall have high impact to IC industry to provide post-scaling solution.