智慧型眼鏡助聽器---子計畫二：影像輔助語音處理

Abstract

本群計畫將設計並實現一個智慧型眼鏡助聽器。「子計畫二」發展所需的語音訊號 處理加速器設計與利用智慧型眼鏡提供的影像資訊來輔助語音處理加速器設計。語音訊 號處理會利用聽覺特性和語音特性發展回音消除、語音偵測、雜訊抑制、動態壓縮演算 法，並藉由影像的輔助來加強語音偵測及雜訊抑制。目前助聽器系統之語音訊號處理以 數位方式的處理為主流再加上本計畫將發展高階助聽器所需之智慧功能，數位式的設計 比較具有可程式性（Programmable）及適應性（Adaptive）。因應助聽器系統之滿意度偏 低，本計畫在華語語音與聲音處理上及近身網路系統上和子計畫一合作，儘量朝提高舒 適性，個性化及環境(Ambient)適應性等智慧功能提出各項系統解決方案。本計畫所設計 的電路皆會以 90 nm的CMOS製程(含driver, mixed-signal 及數位)整合為一個系統晶片。 以1V 電池操作，內部採動態電壓及頻率變動(Dynamic-Voltage-Frequency-Scale)，整體 消耗功率不得超過 1 mW。此規格將比現有之規格更省3 倍以上之功率消耗。 助聽器因其微小化裝置之需求，低功率為其最重要之電性指標之一，故其亦為低電 壓/低功率(LV/LP)之系統架構與電路設計技術的絕佳測試平台，所以在此計畫中，針對 90nm 之製程亦全面將數位及內嵌式SRAM 之LV/LP 技術實現，並整合與帶領此總計畫 之數位部分，以功率與運算比及功率/聲音效能比（效能指標:Performance Index）為本計 畫在數位硬體與語音信號處理之晶片效能指標（Chip Performance Index, CPI）。另外在 整合類比，微機電上亦以整體之系統功率為考量。 本計畫以內嵌式數位信號處理平台，發展各式低功率聽覺信號處理演算法架構與數 位電路設計。本子計畫項目有：(1) 語音處理加速器設計：能夠即時處理語音的回音消 除、雜訊抑制與動態壓縮；(2) 影像輔助語音處理加速器設計。預期研發的技術成果有： 智慧型眼鏡助聽器發展平台，高精準度的語音偵測技術，人類聽覺模型以及華語語音訊 號處理技術，影像輔助之語音訊號處理技術及超低功率/電壓 SoC 設計技術與流程。

The goal of the group project is to design and implement a smart-glass hearing aid system. This subproject (Subproject 2) will develop the speech signal processing accelerator and use the video information to assist this accelerator. The proposed algorithm exploits the human hearing perception and characteristics of speech to develop the feedback cancellation, voice activity detection, noise reduction, and dynamic range compression. The video can assist and improve the voice activity detection and noise reduction. Now digital signal processing for hearing aid system is the mainstream and the subproject needs complicated DSP. Also, digital approach can have programmable and adaptive flexibility. Due to the low satisfaction of hearing aid system, we will work with subproject 1 to propose a comfortable, personalized and ambient awareness hardware solution for smart-glass hearing aid system. Also, the whole hearing aid design platform will be set up including body area network. This hearing aid system will use 90 nm CMOS process (including driver, mixed-signal, and digital circuit) with 1V power supply and dynamic-voltage-frequency-scale to integrate all subsystem into one SoC to achieve less than 1mW power consumption. The power consumption can be reduced to about one of third times of current hearing aid. Due to the miniature requirement of the system, low-power consumption is the most important index in system design. Thus, it is also the best testing platform for LV/LP. The subproject will use 90 nm CMOS process with embedded SRAM for LV/LP. Performance index of power/computation and power/speech processing performance will be the major chip performance index. Moreover, the low power consumption is also the main consideration for the chip integration with analog circuit and MEMS. The major techniques that will develop in this subproject are (1) Mandarin and ambient awareness speech digital processing accelerator: feedback cancellation, noise reduction and dynamic range compression; (2) video-assisted digital speech processing accelerator. The expected results are smart-glass hearing aid system development platform, high-accuracy voice activity detection, human hearing model and Mandarin/speech processing algorithm, video-assisted speech processing algorithm and ultra-low-power SoC design techniques and design flow.