具高微縮性及陡峭次臨界擺幅之全包覆式閘極無接面電晶體研究開發

Title:	具高微縮性及陡峭次臨界擺幅之全包覆式閘極無接面電晶體研究開發 Investigation of Gate-All-Around Junctionless Transistor Featuring High Scalability and Steep Subthreshold Swing
Authors:	張俊彥鄭淳護國立交通大學電子工程學系及電子研究所
Keywords:	;
Issue Date:	2016
Abstract:
Gov't Doc #:	MOST105-2221-E009-140-MY3
URI:	https://www.grb.gov.tw/search/planDetail?id=11882040&docId=486133 http://hdl.handle.net/11536/131816
Appears in Collections:	Research Plans